It is known that clocked components may consume a significant proportion of the total dynamic power of a functional unit, often in a range of 30%-50%. Dual Edge Triggering (DET) is a known technique for reducing the number of clock transitions, and thereby the power consumption, of clocked components. Unlike the more traditional Single Edge Triggering (SET), in which clocked components are triggered on just a single (e.g. rising or falling) transition edge of a clock signal, DET clocked components are triggered by both the rising and falling transition edges of the clock signal. In this manner, the clock signal may comprise half the transitions whilst still maintaining the same triggering rate for the clocked components. As a result, a power saving may be made in the region of 15%-25% of the total dynamic power of a function unit.
Another known technique for reducing the number of clock transitions of clocked components is to employ clock gating, whereby a clock signal for a clocked component may be ‘gated’, or frozen, when the toggling of the clocked component is not required. In this manner, power is not wasted by driving a clock signal for an idle component. Whilst the combination of clock gating with SET functional units is relatively simple to implement, the same is not true for the use of clock gating with DET functional units.
Another important usage of the clock gating technique is so called functional clock gating, where the sampling operations in the clocked components are blocked in order to obtain specific logic functionality, such as a stall of a core in a microprocessor unit when accessing a memory element etc. In this case, a strict number of blocked sampling operations, as well as their timing, is important, in contrary to the power saving clock gating.
FIG. 1 illustrates some of the problems encountered when clock gating is used in conjunction with DET functional units. Firstly, there is illustrated a full rate, or SET, clock signal CK 100. The SET clock signal CK 100 has been gated, or frozen, for one full rate clock cycle, as illustrated at 105. Accordingly, for the period illustrated, two sampling points 110, 115 are provided by the SET clock signal CK 100, instead of the three sampling points that would otherwise be provided without any gating.
Also illustrated is a first half rate, or DET, clock signal CKD 120. In the same manner as for the SET clock signal CK 100, the first DET clock signal CKD 120 has also been gated by the same apparatus (as the signal CK 100) for the same period of time. However, as can be seen, because of the half rate of the DET clock signal CKD, the DET clock signal CKD 120 misses not just the gated transition, but also the subsequent transition, since it already comprises the required state. Accordingly, for the period illustrated in FIG. 1, only one sampling point 125 is generated by the DET clock signal CKD 125, as opposed to the two generated by the SET clock signal CK 100. As a result, the un-gating of a DET clock signal in this manner can result in a latency of up to a complete half-rate clock cycle (two full-rate clock cycles).
A second half rate, or DET, clock signal CKD 130 is also illustrated in FIG. 1. Once again, the second DET clock signal CKD 130 has been gated for the same period of time. For this second DET clock signal CKD 130, when the clock signal 130 is un-gated, the clock signal is corrected in order to compensate for the clock signal 130 having an incorrect state. Accordingly, no transitions are missed, and the clock signal provides the two required sampling points 135, 140. However, in correcting the clock signal in order to compensate for the clock signal having the incorrect state, an additional transition is created, thereby generating a third, unwanted sampling point 145.
As will be appreciated by a skilled artisan, it is desirable not only to develop new clocked devices that utilise dual edge triggering in combination with clock gating, but also to be able to adapt existing single edge triggering clocked designs for use in dual edge triggering, clock gated components. However, the missing or unwanted sampling points resulting from gating dual edge triggering clock signals described above would likely require a significant re-design, especially considering the functional clock gating.
Typically, clock component circuit design is performed using a Register Transfer Level (RTL) description to describe the operation of synchronous digital circuits. In RTL design, a circuit's behaviour is defined in terms of the flow of signals (or transfer of data) between registers and the logical operations performed on those signals. Typically, RTL abstraction libraries are used within a hardware description language in order to simplify the design of clocked circuits by translating the logical operations to be performed into a gate level representation. However, as will be appreciated, the missing or unwanted sampling points resulting from gating dual edge triggering clock signals described above means that existing RTL libraries used for SET circuit design cannot be used for DET circuit design. Consequently, for DET circuit design, RTL modification is required on a more global level throughout the RTL libraries, which would also require long and costly logical verification.
FIG. 2 illustrates a proposed prior art solution to the problem of a gating cell causing missing and/or unwanted sampling points in a DET clock signal. The solution comprises a DET flip-flop 200 and an inverter 210. The DET flip-flop 200 receives a clock signal (clk) at its clock terminal and a gating signal at its enable terminal. The gating signal is ‘active low’ and ‘inactive high’. The DET flip-flop 200 outputs a gated clock signal (Clkout) from its output terminal. Inverter 210 is connected to the output terminal and to a data terminal of the DET flip-flop 200 as illustrated. When the gating signal is inactive, the DET flip-flop outputs the value provided to its data terminal by the inverter 210 at each transition of the clock signal (clk). The inverter 210 inverts the signal. In this manner, whilst the gating signal is inactive, each transition of the clock signal causes the DET flip-flop to invert its output signal, and thus generate an output clock signal. However, when the gating signal becomes active, the DET flip-flop is gated, effectively freezing its output until the gating signal becomes inactive again, irrespective of the clock signal.
In this manner, the gating cell of FIG. 2 uses a flexible gated clock polarity, whereby the polarity of the gated clock signal (Clkout) is not dependent on the polarity of the input clock sign (clk). As a result, in theory, a transition should not be missed due to the output clock signal comprising an incorrect polarity, nor an extra transition created when attempting to correct for an incorrect polarity of the output clock signal.
FIG. 3 illustrates an example of the timing signals for the gating cell of FIG. 2. As can be seen, initially, whilst the enable signal 310 is inactive (high), the output (Q) 320 of the DET flip-flop 200 of FIG. 2 generally follows the input clock signal 300. The inverter 210 of FIG. 2 generates an inverted version of the output signal 330, which is provided to the input (D) 340 of the DET flip-flop.
In a practical implementation of the DET flip-flop 200, when the enable signal 310 is made active, the DET flip-flop 200 may gate the output signal in one of two ways. Firstly, and as illustrated in FIG. 3, the DET flip-flop 200 may internally “freeze” the data input 340. However, a problem with this approach is that, when the enable signal 330 is subsequently made active after the freezing of the data input 340, the data input 340 may have already taken on the inverted value of the output signal 320, as illustrated at 342. As a result, at the next clock transition, the output signal 322 may take on the now frozen value at the data input 340, as illustrated at 322. As a result, the output signal 320 may comprise an unwanted transition at 322 after the enable signal is made active. Furthermore, upon deactivation of the enable signal 310, since the output signal 320 will have transitioned after the input signal 340 was frozen, the output signal already equals the input signal. Consequently, if the enable signal is deactivated just before a transition within the clock signal 300, the increased (due to the freezing circuit components) delay in the input signal transitioning to the value provided by the inverter 210 may be sufficient to cause the output signal not to transition in time. In the other words, timing constraints to the enable signal, referring to the clock signal, may be unacceptably difficult. Accordingly, a transition in the output may be missed 325 following deactivation of the enable signal. Thus, this manner of gating the DET flip-flop 200 may still result in unwanted transitions, or a latency of up to a complete full rate clock cycle. In any case, such a circuit would not be able to gate one edge of the raw clock signal 300, making it unsuitable for functional clock gating.
As previously mentioned, in a practical implementation of the DET flip-flop 200 of FIG. 2, when the enable signal 310 of FIG. 3 is made active, the DET flip-flop 200 may gate the output signal in one of two ways. The second manner in which the DET flip-flop 200 may gate the output signal is by internally disabling the clock input signal. However, this would be equivalent to the initial DET clock gating problem stated above, and therefore would suffer from the same problems as illustrated in FIG. 1.
Thus, the proposed solution illustrated in FIG. 2 would still require a significant (re)design effort at the Register Transfer Level (RTL).